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| ds07-13606-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l mb90620a series MB90622A/623a/p623a n description the mb90620a series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing, proving to be suitable for various industrial machines, camera and video devices, oa equipment, and for process control. the cpu used in this series is the f 2 mc*-16l. the instruction set for the f 2 mc-16l cpu core is designed to be optimized for controller applications while inheriting the at architecture of the f 2 mc-16/16h series, allowing a wide range of control tasks to be processed efficiently at high speed. the peripheral resources integrated in the mb90620a series include: the uart (clock asynchronous/ synchronous transfer) 1 channel, the extended serial i/o interface 1 channel, the a/d converter (8/10-bit precision) 4 channels, the 16-bit ppg timer (pwm/single-shot function) 2 channels, the 16-bit reload timer 3 channels, the 16-bit free-run timer (built-in compare register: 2 channels) 2 channels, the external interrupt 8 channels, the watch timer 1 channel, lcd controller/driver 32 segments 4 commons. *: f 2 mc stands for fujitsu flexible microcontroller. n features f 2 mc-16l cpu ? minimum execution time: 83.33 ns (at machine clock frequency of 12 mhz) ? dual-clock control systems ? pll clock control (continued) n package 100-pin plastic lqfp (fpt-100p-m05)
mb90620a series 2 (continued) ? instruction set optimized for controller applications variety of data types: bit, byte, word, long-word expanded addressing modes: 23 types high coding efficiency improvement of high-precision arithmetic operations through use of 32-bit accumulator ? instruction set supports high-level language (c language) and multitasking inclusion of system stack pointer enhanced pointer-indirect instructions barrel shift instruction ? improved execution speed: 4-byte instruction queue ? 8-level, 32-factor powerful interrupt service functions ? automatic transfer function independent of cpu (ei 2 os) ? general-purpose ports: max. 59 channels ? 18-bit timebase timer/15-bit watch timer ? watchdog timer function ? cpu intermittent operation function ? various standby modes peripheral blocks ? rom:32 kbytes (MB90622A) 48 kbytes (mb90623a) ? one-time prom: 48 kbytes (mb90p623a) ? ram: 1.64 kbytes (MB90622A) 2 kbytes (mb90623a/p623a) ? general-purpose ports: max. 59 channels ? dual-clock control system ? pll clock multiplication control system ? uart: 1 channel can be used for either asynchronous transfer or synchronous transfer with clock ? extended serial i/o interface: 1 channel can be used for 8-bit synchronous transfer ? a/d converter (8/10-bit resolution): 4 channels ? ppg (programable pulse generator): 2 channels ? 16-bit reload timer: 3 channels ? 16-bit free-run timer: 2 channels with compare register 2 channels ? lcd controller/driver 32 segments, 4 commons ? external interrupts: 8 channels ? 18-bit timebase timer ? 15-bit watch timer ? watchdog timer function ? cpu intermittent operation function ? standby mode watch mode sleep mode stop mode 3 mb90620a series n product lineup mb90623a mb90p623a classification mass production products (mask rom products) one-time model rom size 32 kbytes 48 kbytes 48 kbytes ram size 1.64 kbytes 2 kbytes 2 kbytes cpu functions number of instructions: 340 instruction bit length: 8 or 16 bits instruction length: 1 to 7 bytes data bit length: 1, 4, 8, 16, or 32 bits minimum execution time: 83.33 ns at 12 mhz (internal) oscillation circuit dual-clock system of main clock and sub clock ports uart number of channels: 1 clock synchronous communication (1202 to 9615 bps, full-duplex double buffering) clock asynchronous communication (62.5 k to 1 m bps, full-duplex double buffering) supports multiprocessor mode serial number of channels: 1 internal or external clock mode clock synchronous transfer (62.5 khz to 1 mhz, lsb first or msb first transfer) a/d converter resolution: 10 or 8 bits, number of input channels: 4 single-conversion mode (conversion for a specified input channel) scan conversion mode (continuous conversion for specified consecutive channels) continuous conversion mode (repeated conversion for a specified channel) stop conversion mode (periodical conversion) timer number of channels: 3 16-bit reload timer operation (operation clock: sub/2, f /2 3 , f /2 5 , external) free-run timer number of channels: 2 16-bit up-counter (four types of count clocks) 2 channels on each timer of the compare register (compare matching interrupt available) ppg timer number of channels: 2 pwm function, single-shot function with external trigger function lcd controller /driver common output: 4 channels, segment output: 32 channels direct driving of the lcd module 16 bytes of data memory for display operation clock source (main clock/sub clock selective) standby modes stop mode, sleep mode, and watch mode pll functions main clock multiplication ( 1, 2, 3 and 4) package fpt-100p-m05 MB90622A max. 59 channels i/o ports (cmos): 17 i/o ports (cmos) with pull-up resistor available: 24 i/o ports (open drain): 18 parameter part number mb90620a series 4 n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p76/seg30 p75/seg29 p74/seg28 p73/seg27 p72/seg26 p71/seg25 p70/seg24 p67/seg23 p66/seg22 p65/seg21 p64/seg20 p63/seg19 p62/seg18 p61/seg17 p60/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg09 seg08 seg07 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22 p23 p24/sin0 p25/sot0 p26/sck0 p27/ckot p30/sin1 p31/sot1 v ss p32/sck1 p33 p34 p35 p36 p37/trg/atg p40/ppg0 p41/ppg1 p42/int7/tio0 p43/tio1 p44/tio2 v cc p45 p46 v0 v1 v2 v3 com0 com1 com2 com3 av cc avrh avrl av ss p50/an0 p51/an1 p52/an2 p53/an3 v ss seg00 seg01 seg02 seg03 seg04 seg05 md0 md1 md2 seg06 p21 p20 p17 p16 p15 p14 p13 p12 p11 p10 p07 p06/int6 p05/int5 p04/int4 p03/int3 p02/int2 p01/int1 p00/int0 v cc x1 x0 v ss x0a x1a seg31/p77 (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (fpt-100p-m05) 5 mb90620a series n pin description (continued) pin no. pin name circuit type function 77 78 x1a x0a a (oscillation) crystal oscillator pins (32 khz) 79 v ss power supply digital circuit power supply (gnd) pin 80 81 x0 x1 a (oscillation) crystal/far oscillator pins (4 mhz) 82 v cc power supply digital circuit power supply pin 83 to 89 p00 to p06 m (cmos/h) general-purpose i/o ports at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. int0 to int6 external interrupt request input pins when external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. 90 p07 g (cmos) general-purpose i/o port at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. 91 to 98 p10 to p17 g (cmos) general-purpose i/o ports at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. 99, 100 1, 2 p20 to p23 g (cmos) general-purpose i/o ports at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. 3p24 f (cmos/h) general-purpose i/o port at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. sin0 uart serial data input pin during uart input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. 4p25 g (cmos) general-purpose i/o port at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. sot0 uart serial data output pin this function is available when the uart serial data output is enabled. 5p26 f (cmos/h) general-purpose i/o port at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. sck0 uart serial data i/o pin this function is available when the uart clock output is enabled. during uart input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. mb90620a series 6 (continued) pin no. pin name circuit type function 6p27 g (cmos) general-purpose i/o port at this pin, a pull-up resistor is added in the input mode depending on the settings of the pull-up resistor setting register. ckot clock output pin this function is available when clock output is enabled. 7p30 e (cmos/h) general-purpose i/o port sin1 i/o extended serial data input pin this pin, as required, is used for input during input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 8p31 d (cmos) general-purpose i/o port sot1 i/o extended serial data output pin this function is available when serial data data output is enabled. 9v ss power supply digital circuit power supply (gnd) pin 10 p32 e (cmos/h) general-purpose i/o port sck1 i/o extended serial clock i/o pins this function is available when clock input is enabled. this pin, as required, is used for input during input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 11 to 14 p33 to p36 d (cmos) general-purpose i/o ports 15 p37 e (cmos/h) general-purpose i/o port trg ppg0 and ppg1 external trigger input pin atg a/d converter trigger input pin during a/d converter input operations, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. 16 p40 d (cmos) general-purpose i/o port this function is available when ppg timer 0 output is disabled. ppg0 ppg timer 0 output pin this function is available when the ppg timer 0 waveform output is enabled. 17 p41 d (cmos) general-purpose i/o port this function is available when ppg timer 1 output is disabled. ppg1 ppg timer 1 output pin this function is available when the ppg timer 1 waveform output is enabled. 7 mb90620a series (continued) pin no. pin name circuit type function 18 p42 l (cmos/h) general-purpose i/o port this function is available when the timer output from timer 0 is disabled. int7 external interrupt request input pin when external interrupts are enabled, these inputs may be used at any time; therefore, it is necessary to stop output by other functions on these pins, except when using them for output deliberately. tio0 timer input pin the data on this pin is used as event count signal for timer 0. timer output pin this function is available when the timer output from timer 0 is enabled. 19 p43 e (cmos/h) general-purpose i/o port this function is available when the timer output from timer 1 is disabled. tio1 timer input pin the data on this pin is used as event count signal for timer 1. timer output pin this function is available when the timer output from timer 1 is enabled. 20 p44 e (cmos/h) general-purpose i/o port this function is available when the timer output from timer 2 is disabled. tio2 timer input pin the data on this pin is used as event count signal for timer 2. timer output pin this function is available when the timer output from timer 2 is enabled. 21 v cc power supply digital circuit power supply pin 22, 23 p45, p46 h (cmos) open-drain i/o ports 24 to 27 v0 to v3 power supply lcdc reference power supply pins 28 to 31 com0 to com3 k lcdc common pins 32 av cc power supply analog circuit power supply pin this power supply must only be turned on or off when electric potential of av cc or greater is applied to v cc . 33 avrh power supply analog circuit reference voltage input pin this pin must only be turned on or off when electric potential of avrh or greater is applied to av cc . 34 avrl power supply analog circuit reference voltage input pin 35 av ss power supply analog circuit power supply (gnd) pin mb90620a series 8 (continued) pin no. pin name circuit type function 36 to 39 p50 to p53 i (ad) general-purpose i/o ports this function is available when port is specified in the analog input enable register. an0 to an3 a/d converter analog input pins this function is available when the analog input enable register specification is ad. 40 v ss power supply digital circuit power supply (gnd) pin 41 to 46 seg00 to seg05 k lcdc segment-only pins 47 to 49 md0 to md2 c (cmos) operating mode selection input pins connect directly to v cc or v ss . 50 to 59 seg06 to seg15 k lcdc segment-only pins 60 to 67 p60 to p67 j open-drain i/o ports this is available when enabled by the lcr2. seg16 to seg23 lcdc segment pins 68 to 74 p70 to p76 j open-drain i/o ports this is available when enabled by the lcr2. seg24 to seg30 lcdc segment pins 75 rst b (cmos/h) external reset request input pin 76 p77 j open-drain i/o port this is available when enabled by the lcr2. seg31 lcdc segment pin 9 mb90620a series n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistor: approximately 1 m w b ? hysteresis input with pull-up resistor c?cmos input port d ? cmos level input/output e ? cmos level output ? hysteresis input x1 (a) x0 (a) standby control signal v ss diffused resistor cmos v cc digital output digital output standby control signal standby control signal mb90620a series 10 (continued) type circuit remarks f ? with input pull-up resistor control ? cmos level output ? hysteresis input g ? with input pull-up resistor control ? cmos level input/output h ? open-drain type input/output i ? cmos level input/output ? analog input pull-up control standby control signal cmos pull-up control standby control signal cmos standby control signal cmos analog input standby control signal 11 mb90620a series (continued) type circuit remarks j ? open-drain type output ? cmos level input ? combined with the lcd output k ? lcd output pin l ? cmos level output ? hysteresis input m ? with input pull-up resistor control ? cmos level output ? hysteresis input standby control signal cmos lcd output lcd output lcd output lcd output pull-up controller mb90620a series 12 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to the input and output pins other than medium- and high voltage pins or if higher than the voltage is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. 2. treatment of unused pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistors. 3. external reset input to reset the internal circuit by the low-level input to the rst pin, the low-level input to the rst pin must be maintained for at least five machine cycles. pay attention to it if the chip uses external clock input. 4. v cc and v ss pins apply equal potential to the v cc and v ss pins. 5. precautions when using an external clock when an external clock is used, drive x0 pin. 6. sequence for applying a/d converter power supply and analog inputs be sure to turn on the digital power supply (v cc ) before applying the a/d converter power supply (av cc , avrh, and avrl) and the analog inputs (an0 to an15). in addition, when the power is turned off, turn off the a/d converter power supply (av cc , avrh, and avrl) and the analog inputs (an0 to an15) first, and then turn off the digital power supply (av cc ). whether applying or cutting off the power, be certain that avrh does not exceed av cc . 7. program mode in the mb90p623, all of the bits (48 k 8 bits) are set to 1 when the ic is shipped from fujitsu and after erasure. to input data, program the ic by selectively setting the desired bits to 0. bits cannot be set to 1 electrically. x0, (x0a) x1, (x1a) mb90620a ? using of external clock 13 mb90620a series 8. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom width microcontroller program. 9. programming yield all bit cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. program, verify aging +150 c, 48 hrs. data verification assembly mb90620a series 14 n programming to the eprom on the mb90p623a in eprom mode, the mb90p623 eprom functions equivalent to the mbm27c1000. this allows the prom to be programmed with a general-purpose eprom programmer by using the dedicated socket adapter. 1. eprom mode pin assignments mbm27c1000 compatible pins mbm27c1000 mb90p623a pin no. pin name pin no. pin name 1v pp 49 md2 (v pp ) 2 oe* 10 p32 3a1598p17 4a1295p14 5a076p27 6a065p26 7a054p25 8a043p24 9a032p23 10 a02 1 p22 11 a01 100 p21 12 a00 99 p20 13 d00 83 p00 14 d01 84 p01 15 d02 85 p02 16 gnd* mbm27c1000 mb90p623a pin no. pin name pin no. pin name 32 v cc 31 pgm 11 p33 30 n.c. 29a1497p16 28a1396p15 27a0891p10 26a0992p11 25a1194p13 24 a16 7 p30 23a1093p12 22 ce 8 p31 21a0790p07 20 d06 89 p06 19 d05 88 p05 18 d04 87 p04 17 d03 86 p03 * : connect a capacitance of 20 pf across oe (pin no.2) and gnd (pin no.16) pins of the mbm27c1000. power supply, gnd connection pins classification pin no. pin name power supply 21 82 v cc v cc gnd 9 34 35 40 75 79 12 13 14 v ss avrl av ss v ss rst v ss p34 p35 p36 15 mb90620a series 2. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 part no. package compatible socket adapter sun hayato co., ltd. mb90p623apfv sqfp-100 rom-100sqf-32dp-16l non-mbm27c1000 compatible pins pin no. pin name treatment 47 48 80 78 md0 md1 x0 x0a 81 77 28 to 31 41 to 46 50 to 59 x1 x1a com0 to com3 seg00 to seg05 seg06 to seg15 15 16 to 20 22 23 24 to 27 32 33 36 to 39 60 to 74 76 p37 p40 to p44 p45 p46 v0 to v3 av cc avrh p50 to p53 p60 to p76 p77 connect a pull-up resistor of 4.7 k w open connect a pull-up resistor of about 1 m w to each pin. mb90620a series 16 3. programming procedure (1) set the eprom programmer to the mbm27c1000. (2) load the program data into the eprom programmer at 14000 h to 1ffff h . the rom addresses from ff4000 h to ffffff h in operating mode of mb90p623a series correspond to 14000 h to 1ffff h in eprom mode. (3) insert the mb90p623a in the socket adapter, and mount the socket adapter on the eprom programmer. pay attention to the orientation of the device and of the socket adapter when doing so. (4) activate the programming. (5) if programming cannot be performed successfully, connect a 0.1 m f or similar capacitor between v cc and gnd and between v pp and gnd. note: because the mask rom products (mb90623a) do not have an eprom mode, they cannot read data from the eprom programmer. ffffff h 1ffff h 14000 h eprom mode operating mode eprom eprom ff4000 h 17 mb90620a series n block diagram clock controller ram interrupt controller 8 8 8 8 7 4 8 8 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p46 p50 to p53 p60 to p67 p70 to p77 i/o ports cpu f 2 mc-16l rom external interrupt free-run timer 2 compare register 8 int0 to int7 6 x0, x1 rst x0a, x1a md0 to md2 ppg0, ppg1 trg lcd controller/driver seg00 seg31 v0 to v3 com0 to com3 to timer 3 a/d converter av cc avrh, avrl av ss atg an0 to an3 sin0 sot0 sck0 ckot sin1 sot1 sck1 tio0 to tio2 ppg 2 uart communication prescaler extended serial i/o interface 2 4 3 2 40 f 2 mc-16l bus + ? p00 to p27 (24 channels): input pull-up resistor setting enable pins ? p45, p46, p60 to p77 (18 channels): open-drain pins mb90620a series 18 n memory map : internal access : no access rom area rom area (ff bank image) ram register peripherals ffffff h address#1 ff0000 h 010000 h address#2 004000 h 002000 h 000100 h 0000c0 h 000000 h address#3 address #3 address #2 address #1 product MB90622A mb90623a mb90p623a ff8000 h ff4000 h ff4000 h 008000 h 004000 h 004000 h 000780 h 000900 h 000900 h note: while the rom data image of bank ff can be seen in the upper portion of bank 00, this is done only to permit effective use of the c compilers small model. because the lower 16 bits of bank ff address and the lower 16 bits of bank 00 are the same, it is possible to reference tables in rom without declaring the far specification in the pointer. 19 mb90620a series n i/o map (continued) address register register name access resource name initial value 000000 h port 0 data register pdr0 r/w port 0 x x x x x x x x 000001 h port 1 data register pdr1 r/w port 1 x x x x x x x x 000002 h port 2 data register pdr2 r/w port 2 x x x x x x x x 000003 h port 3 data register pdr3 r/w port 3 x x x x x x x x 000004 h port 4 data register pdr4 r/w port 4 C x x x x x x x 000005 h port 5 data register pdr5 r/w port 5 C C C C x x x x 000006 h port 6 data register pdr6 r/w port 6 x x x x x x x x 000007 h port 7 data register pdr7 r/w port 7 C x x x x x x x 000008 h to 0f h vacancy* 000010 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 000011 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 000012 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 000013 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 000014 h port 4 direction register ddr4 r/w port 4 C 0 0 0 0 0 0 0 000015 h port 5 direction register ddr5 r/w port 5 C C C C 0 0 0 0 000016 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 000017 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 000018 h to 19 h vacancy* 00001a h port 0 pull-up resistor setting register rdr0 r/w port 0 0 0 0 0 0 0 0 0 00001b h port 1 pull-up resistor setting register rdr1 r/w port 1 0 0 0 0 0 0 0 0 00001c h port 2 pull-up resistor setting register rdr2 r/w port 2 0 0 0 0 0 0 0 0 00001d h analog input enable register ader r/w a/d C C C C 1 1 1 1 00001e h clock output enable register ckot r/w clock output (ckot) CCCC0000 00001f h vacancy* 000020 h serial mode register smr r/w uart 00000000 000021 h serial control register scr r/w 0 0 0 0 0 1 0 0 000022 h serial input register/ serial output register sidr/ sodr r/w xxxxxxxx 000023 h serial status register ssr r/w 0 0 0 1 C C 0 0 000024 h serial mode control status register smcs r/w extended serial i/o interface CCC00000 000025 h 00000010 000026 h serial data register sdr r/w x x x x x x x x mb90620a series 20 (continued) address register register name access resource name initial value 000027 h communication prescaler control register cdcr r/w uart, i/o, serial 0 C C C 1 1 1 1 000028 h dtp/interrupt enable register enir r/w dtp/external interrupt 00000000 000029 h dtp/interrupt source register eirr r/w 0 0 0 0 0 0 0 0 00002a h request level setting register elvr r/w 00000000 00002b h 00000000 00002c h a/d control status register adcs0 r/w 8/10-bit a/d converter 00000000 00002d h adcs1 00000000 00002e h a/d data register adcr0 r/w xxxxxxxx 00002f h adcr1 000000xx 000030 h ppg0 cycle setting register pcsr0 w 16-bit ppg timer 0 xxxxxxxx 000031 h xxxxxxxx 000032 h ppg0 duty factor setting register pdut0 w xxxxxxxx 000033 h xxxxxxxx 000034 h ppg0 control status register pcnl0 r/w 00000000 000035 h pcnh0 0000000C 000036 h to 37 h vacancy* 000038 h ppg1 cycle setting register pcsr1 w 16-bit ppg timer 1 xxxxxxxx 000039 h xxxxxxxx 00003a h ppg1 duty factor setting register pdut1 w xxxxxxxx 00003b h xxxxxxxx 00003c h ppg1 control status register pcnl1 r/w 00000000 00003d h pcnh1 0000000C 00003e h , 3f h vacancy* 000040 h timer control status register tmcsr0 r/w 16-bit reload timer 0 00000000 000041 h CCCC0000 000042 h 16-bit timer register tmr0 r/w xxxxxxxx 000043 h xxxxxxxx 000044 h 16-bit reload register tmrlr0 r/w xxxxxxxx 000045 h xxxxxxxx 21 mb90620a series (continued) address register register name access resource name initial value 000046 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 000047 h CCCC0000 000048 h 16-bit timer register 1 tmr1 r/w xxxxxxxx 000049 h xxxxxxxx 00004a h 16-bit reload register 1 tmrlr1 r/w xxxxxxxx 00004b h xxxxxxxx 00004c h to 4f h vacancy* 000050 h timer control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 000051 h CCCC0000 000052 h 16-bit timer register 2 tmr2 r/w xxxxxxxx 000053 h xxxxxxxx 000054 h 16-bit reload register 2 tmrlr2 r/w xxxxxxxx 000055 h xxxxxxxx 000056 h timer data register 0 tcdt0 r 00000000 000057 h 00000000 000058 h timer control status register 0 tcs0 r/w 0 0 0 0 0 0 0 0 000059 h compare control status register 0 ccs0 r/w 0 0 0 0 C C 0 0 00005a h timer 0 compare register 0 tcr00 r/w xxxxxxxx 00005b h xxxxxxxx 00005c h timer 0 compare register 1 tcr01 r/w xxxxxxxx 00005d h xxxxxxxx 00005e h , 5f h vacancy* 000060 h timer data register 1 tcdt1 r 00000000 000061 h 00000000 000062 h timer control status register 1 tcs1 r/w 0 0 0 0 0 0 0 0 000063 h compare control status register 1 ccs1 r/w 0 0 0 0 C C 0 0 000064 h timer 1 compare register 0 tcr10 r/w xxxxxxxx 000065 h xxxxxxxx 000066 h timer 1 compare register 1 tcr11 r/w xxxxxxxx 000067 h xxxxxxxx compare register block compare register block 16-bit free-run timer 0 16-bit free-run timer 1 mb90620a series 22 (continued) address register register name access resource name initial value 000068 h to 6f h vacancy* 000070 h to 7f h lcd display data ram vram r/w lcd controller/ driver xxxxxxxx xxxxxxxx 000080 h lcdc control register 0 lcr0 r/w 00010000 000081 h lcdc control register 1 lcr1 0 C C 0 0 0 0 0 000082 h to 8f h vacancy* 000090 h to 9e h system reserved area* 00009f h delayed interrupt source generation/ release register dirr r/w delayed interrupt generation module CCCCCCC0 0000a0 h low-power consumption mode control register lpmcr r/w low-power consumption 00011000 0000a1 h clock selection register ckscr r/w 1 1 1 1 1 1 0 0 0000a2 h to a7 h vacancy* 0000a8 h watchdog timer control register wdtc r/w watchdog timer x x x x x x x x 0000a9 h timebase timer control register tbtc r/w timebase timer 1 C C 0 0 0 0 0 0000aa h watch timer control register wtc r/w watch timer 1 x C 0 0 0 0 0 0000ab h to af h vacancy* 0000b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 0000b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 0000b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 0000b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 0000b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 0000b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 0000b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 0000b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 0000b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 0000b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 0000ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 0000bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 0000bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 0000bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 23 mb90620a series (continued) * : access prohibited. explanation of initial values 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. x: the initial value of this bit is undefined. C: this bit is not used. no initial value is defined. address register register name access resource name initial value 0000be h interrupt control register 14 icr14 r/w interrupt controller 00000111 0000bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 0000c0 h to ff h vacancy* mb90620a series 24 n interrupt sources and their interrupt vectors and interrupt control registers : the request flag is cleared by the i 2 os interrupt clear signal (without stop requests). : the request flag is cleared by the i 2 os interrupt clear signal (with stop requests). : the request flag is not cleared by the i 2 os interrupt clear signal. note: do not set i 2 os startup in an icr xx that does not support i 2 os. interrupt source i 2 os support interrupt vector interrupt control register no. address icr address reset #08 08 h ffffdc h int9 instruction #09 09 h ffffd8 h exception #10 0a h ffffd4 h external interrupt #0 #11 0b h ffffd0 h icr00 0000b0 h external interrupt #1 #12 0c h ffffcc h external interrupt #2 #13 0d h ffffc8 h icr01 0000b1 h external interrupt #3 #14 0e h ffffc4 h external interrupt #4 #15 0f h ffffc0 h icr02 0000b2 h external interrupt #5 #16 10 h ffffbc h external interrupt #6 #17 11 h ffffb8 h icr03 0000b3 h external interrupt #7 #18 12 h ffffb4 h extended serial i/o interface #19 13 h ffffb0 h icr04 0000b4 h free-run timer 0 overflow #21 15 h ffffa8 h icr05 0000b5 h free-run timer 1 overflow #22 16 h ffffa4 h free-run timer 0 and compare register 0 matched #23 17 h ffffa0 h icr06 0000b6 h free-run timer 0 and compare register 1 matched #24 18 h ffff9c h free-run timer 1 and compare register 0 matched #25 19 h ffff98 h icr07 0000b7 h free-run timer 1 and compare register 1 matched #26 1a h ffff94 h ppg timer #0 #27 1b h ffff90 h icr08 0000b8 h ppg timer #1 #28 1c h ffff8c h 16-bit reload timer #0 #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer #1 #30 1e h ffff84 h 16-bit reload timer #2 #31 1f h ffff80 h icr10 0000ba h a/d converter measurement complete #33 21 h ffff78 h icr11 0000bb h watch prescaler #35 23 h ffff70 h icr12 0000bc h timebase timer interval interrupt #36 24 h ffff6c h uart 0 transmission complete #37 25 h ffff68 h icr13 0000bd h uart 1 reception complete #39 27 h ffff60 h icr14 0000be h delayed interrupt generation module #42 2a h ffff54 h icr15 0000bf h 25 mb90620a series n peripherals 1. parallel ports the mb90620a series has 59 input/output pins. in the twenty four input/output ports mapped on port 0 to 2, pull-up resistors are selectively added during input state operations depending on the settings in the resistor setting register. p45, p46, port 6 and port 7 are open-drain ports. port 6 and port 7 are combined with the lcd segment pin function. (1) register configuration pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdrx 15 14 13 12 11 10 9 8 76 54 3210 address: port data register pdr1 pdr3 pdr5 pdr7 000001 h 000003 h 000005 h 000007 h bit pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdrx address: port data register pdr0 pdr2 pdr4 pdr6 000000 h 000002 h 000004 h 000006 h bit dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddrx 15 14 13 12 11 10 9 8 76 54 3210 address: port direction register ddr1 ddr3 ddr5 ddr7 000011 h 000013 h 000015 h 000017 h bit rd 7rd 6rd 5rd 4rd 3rd 2rd 1rd 0 rdr1 ader 15 14 13 12 11 10 9 8 address: pull-up resistor setting register 00001b h bit ade3 ade2 ade1 ade0 15 14 13 12 11 10 9 8 address: analog input enable register 00001d h bit rdr0, rdr2 76 54 3210 address: pull-up resistor setting register 00001a h 00001c h bit dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddrx address: port direction register ddr0 ddr2 ddr4 ddr6 000010 h 000012 h 000014 h 000016 h bit rd 7rd 6rd 5rd 4rd 3rd 2rd 1rd 0 notes: bit 7 of port 4 does not have a register bit. bit 4 to bit 7 of port 5 does not have a register bit. notes: bit 7 of port 4 does not have a register bit. bit 4 to bit 7 of port 5 does not have a register bit. mb90620a series 26 (2) block diagram internal data bus data register read data register write direction register read direction register write data register direction register pin internal data bus data register read data register write data register pin rmw (read-modify-write instruction) internal data bus data register read data register write ader register write direction register write data register direction register pin ader re g ister read rmw (read-modify-write instruction) ader ? i/o port ? open-drain port ? port combined with the a/d converter functions 27 mb90620a series bus data register direction register port input/output resistor register pull-up resistor (approx. 50 k w ) ? port with a pull-up resistor option mb90620a series 28 2. uart the uart is a serial i/o port for clk asynchronous (start-stop synchronization) communications or for clk synchronous communications. the features of this module are described below: ? full-duplex double buffer ? clk asynchronous (start-stop synchronization) communications and clk synchronous communications capable ? supports multiprocessor mode ? built-in dedicated baud rate generator ? permits setting of any desired baud rate according to an external clock input ? error detection function (parity errors, framing errors, and overrun errors) ? nrz code as transfer signal ? supports intelligent i/o service (1) register configuration clk asynchronous: 9615, 31250, 4808, 2404, 1202 bps clk synchronous: 1 m, 500k, 250k, 125k, 62.5k bps for a 6, 8, 10, 12, or 16 mhz clock. md1 md0 cs2 cs1 cs0 reserved scke soe serial mode register (smr) 76 54 3210 address: address: 000020 h bit pen p sbl cl a/d rec rxe txe serial control register (scr) 15 14 13 12 11 10 9 8 000021 h bit d7 d6 d5 d4 d3 d2 d1 d0 serial input register serial output register (sidr/sodr) 76 54 3210 address: 000022 h bit address: pe ope fre rdrf tdre rie tie serial status register (ssr) 15 14 13 12 11 10 9 8 000023 h bit address: md div3 div2 div1 div0 communication prescaler control register (cdcr) 15 14 13 12 11 10 9 8 000027 h bit 29 mb90620a series (2) block diagram control signals dedicated baud rate generator 16-bit timer 0 (internally connected) external clock sin0 clock selection circuit reception interrupt (to cpu) transmission interrupt (to cpu) reception control circuit start bit detection circuit reception bit counter transmission control circuit transmission start circuit transmission bit counter transmission parity counter reception parity counter reception status determination circuit reception shifter reception end transmission shifter transmission start reception error generation signal for i 2 os (to cpu) sidr sodr f 2 mc-16l bus smr register md1 md0 cs2 cs1 cs0 scke soe scr register ssr register control signals transmission clock reception clock sot0 pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck0 mb90620a series 30 3. extended serial i/o interface this block consists of an 8-bit serial i/o interface that can perform clock synchronous data transfer. either lsb- first or msb-first data transfer can be selected. the serial i/o port to be used can also be selected. the following two serial i/o operation modes are available. internal shift clock mode: data transfer is synchronization with the internal clock. external shift clock mode: data transfer is synchronization with the clock input from the external pin (sck1). by manipulating the general-purpose port that shares the external pin (sck1), this mode also enables the data transfer operation to be driven by cpu instructions. (1) register configuration (2) block diagram address: smd2 smd1 smd0 sie sir busy stop strt serial mode control status register (smcs) serial data register (sdr) 15 14 13 12 11 10 9 8 000025 h bit address: mode bds soe scoe 76 54 3210 000024 h bit address: d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 000026 h bit control circuit internal data bus shift clock counter internal clock transfer direction selection read write interrupt request sin1 sot1 sck1 sdr (serial data register) 10 2 smd2 smd1 smd0 sir sie busy stop strt mode bds soe scoe (msb-first) d0 to d7 d7 to d0 (lsb-first) internal data bus 31 mb90620a series 4. a/d converter the a/d converter converts the analog input voltage into a digital value. the features of this module are as follows: ? conversion time: minimum of 7 m s per channel (12 mhz machine clock) ? rc-type successive approximation conversion method with sample and hold circuit ? 8-bit/10-bit resolution ? analog input is selectable by software from among 4 channels ? a/d conversion mode selectable from the following three: one-shot conversion mode: converts a specified channel once. continuous conversion mode: converts a specified channel repeatedly. stop conversion mode: pauses after converting one channel and wait until the next activation (permits synchronization of start of conversion). ? conversion mode: single-conversion mode: converts one channel (when the start and stop channels are the same). scan conversion mode: converts several consecutive channels (when the start and stop channels are different). ? when a/d conversion is completed, an a/d conversion complete interrupt request can be issued to the cpu. because generating this interrupt can be used to activate the i 2 os and transfer the a/d conversion results to memory, this function is suitable for continuous processing. ? activation sources can be selected from among software, an external trigger (falling edge), and timer (rising edge). (1) register configuration address: busy int inte paus sts1 sts0 strt 15 14 13 12 11 10 9 8 00002d h bit md1 md0 ans1 ans0 ane1 ane0 a/d converter control status register (adcs1, adcs0) 76 54 3210 address: 00002c h bit address: 000000d9d8 15 14 13 12 11 10 9 8 00002f h bit address: d7 d6 d5 d4 d3 d2 d1 d0 a/d converter data register (adcr1, adcr0) 76 54 3210 00002e h bit reserved reserved reserved mb90620a series 32 (2) block diagram av cc avrh avrl an0 an1 an2 an3 mpx input circuit sample and hold circuit comparator d/a converter sequential comparison register data register decoder a/d converter control status register 0 a/d converter control status register 1 adcr1, adcr0 adcs1, adcs0 atg reload timer 0 f trigger activation operating clock prescaler data bus av ss 33 mb90620a series 5. 16-bit timer (with event count function) the 16-bit timer consists of a 16-bit down counter, a 16-bit reload register, one input and output pin (tin x ,tot x ), and a control register. three internal clocks and an external clock can be selected for the input clock. when in reload mode, a toggled output waveform is output, while in one-shot mode a square wave indicating that the count is in progress is output pin (tot x ). the input pin (tin x ) serves as an event input in event count mode, and can be used for trigger input or gate input in internal clock mode. (1) register configuration address: : : mod0 oute outl reld inte uf cnte 76 54 3210 000040 h 000046 h 000050 h bit csl1 mod2 mod1 timer control status register 0 to 2 (tmcsr 0 to tmcsr 2 ) 15 14 13 12 11 10 9 8 address: : : 000041 h 000047 h 000051 h bit address: : : 15 0 000042 h 000048 h 000052 h bit 15 0 bit address: : : 16-bit timer register 0 to 2 (tmr 0 to tmr 2 ) 16-bit reload register 0 to 2 (tmrlr 0 to tmrlr 2 ) 000044 h 00004a h 000054 h trg csl0 mb90620a series 34 (2) block diagram 16-bit reload register 16-bit down counter uf clock selector reload reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. 3 internal clock prescaler clear exck gate 2 retrigger irq port (tin) (tout) clear i 2 osclr f 2 mc-16l bus fff 2 1 2 3 2 5 35 mb90620a series 6. 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up counter, a control status register, and a compare register. ? count clock is selectable from 4 types. ? a counter over flow interrupt can be generated. ? an interrupt can be generated on matching with the compare register value. ? initialization of the counter on matching with compare register 0 value is enabled depending on the mode settings. (1) register configuration address: : t15 t14 t13 t12 t11 t10 t09 15 14 13 12 11 10 9 8 000056 h 000060 h bit t07 t06 t04 t03 t01 t00 timer data register 0, 1 (tcdt0, tcdt1) compare control status 0, 1 register (ccs0, ccs1) 76 54 3210 address: : 000059 h 000063 h bit address: : icp1 icp0 ice1 ice0 cst1 cst0 15 14 13 12 11 10 9 8 000058 h 000062 h bit address: : : : reserved ivf ivfe stop mode clr clk1 clk0 timer control status 0, 1 register (tcs0, tcs1) 76 54 3210 00005a h 00005c h 000064 h 000066 h bit t08 t07 t06 t04 t03 t01 t00 t05 t02 c15 c14 c13 c12 c11 c10 c09 c08 15 14 13 12 11 10 9 8 bit c07 c06 c05 c04 c03 c02 c01 c00 timer 0, 1 compare register (tcr00, tcr01/ tcr10, tcr11) 76 54 3210 bit mb90620a series 36 (2) block diagram interrupt request ivf ivfe stop mode clr clk1 clk0 divider f comparator 0 clock compare register x 0 compare register x 1 t00 to t15 t00 to t15 16-bit up-counter bus compare match interrupt compare match interrupt 37 mb90620a series 7. 16-bit ppg timer this module can output a pulse synchronized with an external trigger or a software trigger. in addition, the cycle and duty ratio of the output pulse can be changed as desired by overwriting the two 16-bit register values. pwm function: synchronizes pulse with trigger, and permits programming of the pulse output by overwriting the register values mentioned above. this function permits use as a d/a converter with the addition of external circuits. one-shot function: detects the edge of trigger input, and permits single-pulse output. (1) register configuration address: : cnte stgr mdse rtrg cks1 cks0 pgms 15 14 13 12 11 10 9 8 00035 h 0003d h address: : 00034 h 0003c h bit egs1 egs0 irqf irs1 poen osel ppg0, 1 control status register (pcnh0, pcnh1) ppg0, 1 control status register (pcnl0, pcnl1) 76 54 3210 address: : 00031 h 00039 h bit address: : 15 14 13 12 11 10 9 8 00030 h 00038 h bit address: : ppg0, 1 cycle setting register (pcsr0, pcsr1) ppg0, 1 duty setting register (pdut0, pdut1) 76 54 3210 00033 h 0003b h address: : 00032 h 0003a h bit iren irs0 15 14 13 12 11 10 9 8 bit 76 54 3210 bit mb90620a series 38 (2) block diagram f /2 f /8 f /32 f /128 pcsr pdut 16-bit down-counter ck load start borrow cmp ppg mask ppg output sq r reverse bit interrupt selector irq enable software trigger edge ditection trg input prescaler 39 mb90620a series 8. lcd controller/driver the lcd controller driver consists of the display controller for generating the segment signal and common signal according to data set in the display data memory, the segment driver and the common driver capable of directly driving the lcd panel (liquid crystal display). primary functions are as follows; ? lcd direct drive function ? common output 4 channels (com0 to com3), segment output 32 channels (seg0 to seg31) ? built-in 16 bytes of data memory for display ? duty ratio selective from 1/2, 1/3 and 1/4 ? driving clock source selective from the main clock (4 mhz) and the sub clock (32 khz) ? seg 16 to seg 31 can be used as open-drain ports. (1) register configuration address: : lcr1 lcr0 15 8 7 0 000080 h 000081 h address: 000080 h bit lcd control register lcd display ram lcr0/lcr1 b3 b2 b1 b0 b7 b6 b5 b4 seg00 seg01 seg02 seg03 seg04 seg05 address: 000080 h address: 000080 h address: 000080 h address: 000080 h address: 000080 h address: 000080 h address: 000080 h b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 seg16 seg17 seg18 seg19 b3 b2 b1 b0 b3 b2 b1 b0 b7 b6 b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b1 b0 b7 b6 b5 b4 seg28 seg29 seg30 seg31 b3 b2 b1 b0 b3 b2 b1 b0 b7 b6 b5 b4 b7 b6 b5 b4 com3 com2 com1 com0 b3 b2 b1 b0 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 : : : : : : : : : : : : :: : b5 b4 mb90620a series 40 (2) block diagram 4 mhz 32 khz lcdc control register lcr timing controller common driver ac converter segment driver lcd display ram (16 bytes) controller driver 32 4 power supply input (v0 to v3) internal bus com0 com1 com2 com3 seg27 seg28 seg29 seg30 seg31 seg00 seg01 seg02 seg03 seg04 prescaler 41 mb90620a series 9. dtp/external interrupt the dtp (data transfer peripheral) is a peripheral, positioned between peripherals external to the device and the f 2 mc-16l cpu, that accepts dma requests or interrupt requests generated by external peripherals and transfers them to the f 2 mc-16l cpu to activate the intelligent i/o service or interrupt processing. in the case of the intelligent i/o service, there are two request levels that can be selected: high and low; in the case of an external interrupt request, there are a total of four request levels that can be selected: high, low, rising edge and falling edge. (1) register configuration (2) block diagram 10. watchdog timer, timebase timer, and watch timer functions the watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. the timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. note that the timebase timer uses the main clock, regardless of the setting of the mcs bit and scs bit in ckscr. the watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. note that the watch timer uses the sub clock, regardless of the setting of the mcs bit and scs bit in ckscr. (1) register configuration address: : eirr enir 15 0 000029 h 000028 h bit dtp/interrupt enable register address: : elvr 15 0 00002b h 00002a h bit request level setting register 4 4 4 8 3 dtp/interrupt enable register dtp/interrupt source register request level setting register gate source f/f edge detector request input f 2 mc-16l bus address: 0000a8 h ponr erst srst wt1 wt0 watchdog timer control register (wdtc) timebase timer control register (tbtc) 76 54 3210 address: 0000a9 h bit address: 15 14 13 12 11 10 9 8 0000aa h bit watch timer control register (wtc) 76 54 3210 bit wrst wte wdcs sce wtof wtr wtc1 wtc0 wtie wtc2 reserved tbie tbof tbc1 tbc0 tbr mb90620a series 42 (2) block diagram srst erst wrst ponr wdtc from power-on generation rst pin from rst bit in the stbyc register sub clock wtc wdcs sce wtc2 wtc1 wtc0 wtr wtie wtof and q s r selector q s r and 2 9 2 10 2 11 2 12 2 13 2 14 2 15 wtres 2 10 2 13 2 14 2 15 watch timer clock input scm wdgrst to internal reset generator watchdog reset generator clr 2-bit counter of clr selector wdtc wt1 wt0 wte timebase interrupt tbtc tbc1 tbc0 tbie tbr tbof and q s r selector timebase timer clock input main clock 2 12 2 14 2 16 2 19 tbtres 2 12 2 14 2 16 2 19 f 2 mc-16l bus power-on reset sub clock stops timer interrupt 43 mb90620a series 11. delayed interrupt generation module the delayed interrupt generation module generates task switching interrupts. this module can be used to generate/cancel interrupt requests to the f 2 mc-16l cpu by software. (1) register configuration (2) block diagram delayed interrupt source generation/release register (dirr) address: 00009f h 15 14 13 12 11 10 9 8 bit r0 delayed interrupt source generation/release decoder source latch delayed interrupt generation module interrupt controller write f 2 mc-16l cpu ddir icr yy icr xx cmp il ilm inta cmp f 2 mc-16l bus other requests mb90620a series 44 12. low-power consumption controller (cpu intermittent operation function, oscillation stabilization delay time, clock multiplier function) the following are the operating modes: pll clock mode, pll sleep mode, pll watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. aside from the pll clock mode, all of the other operating modes are low-power consumption modes. in main clock mode and main sleep mode, the main clock (main osc oscillation clock) and the sub clock (sub osc oscillation clock) operate. in these modes, the main clock divided by 2 is used as the operation clock, the sub clock (sub osc oscillation clock) is used as the timer clock, and the pll clock (vco oscillation clock) is stopped. in sub clock mode and sub sleep mode, only the sub clock operates. in these modes, the sub clock is used as the operation clock, and the main clock and pll clock are stopped. in pll sleep mode and main sleep mode, only the cpus operation clock is stopped; all clocks other than the cpu clock operate. in pseudo-watch mode, only the watch timer and timebase timer operate. in pll watch mode, main watch mode, and sub watch mode, only the watch timer operates. in this mode, only the sub clock is used for operation, while the main clock and the pll clock are stopped (the difference between the pll watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt in the pll clock mode, the main clock modes and the sub clock mode respectively, and there is no difference in the watch mode). the main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power. (the difference between the main stop mode and the sub stop mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no difference in the stop mode.) the cpu intermittent operation function intermittently runs the clock supplied to the cpu when accessing registers, on-chip memory, on-chip resources, and the external bus. processing is possible with lower power consumption by reducing the execution speed of the cpu while supplying a hig-speed clock and using on-chip resources. the pll clock multiplier can be selected as either 2, 4, 6, or 8 by setting the cs1 and cs0 bits. these clocks are divided by 2 to be used as a machine clock. the ws1 and ws0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode and hardware standby mode are woken up. (1) register configuration address: 0000a0 h stp slp rst tmd cg0 ssr low-power consumption mode control register (lpmcr) clock selection register (ckscr) 76 54 3210 address: 0000a1 h bit 15 14 13 12 11 10 9 8 bit spl cg1 scm mcm ws0 scs cs1 cs0 ws1 mcs 45 mb90620a series (2) block diagram ckscr scm scs cs1 cs0 cg1 cg0 lpmcr mcm mcs ckscr ckscr slp stp lpmcr tmd ws1 ws0 spl ssr lpmcr ckscr rst lpmcr internal reset generator self-refresh control circuit pin high-impedance controller oscillation stabilization delay time selector 2 4 2 13 2 15 2 18 clock input timebase timer 2 12 2 14 2 16 2 19 pin hi-z self-refresh rst pin internal rst to watchdog timer wdgrst interrupt request or rst sub osc stop main osc stop peripheral clock peripheral clock generation scm standby controller sleep mstp stop rst cancel cpu intermittent operation function cycle count selection circuit cpu clock selector 1/2 s pll multiplier circuit 2 134 sub clock sub clock (osc oscillation) main clock (osc oscillation) cpu clock cpu system clock generation 0/9/17/33 intermittent cycle selection f 2 mc-16l bus switching control mb90620a series 46 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: av cc , avrh and avrl must not exceed v cc . in addition, avrl must not exceed avrh. *2: v i or v o must not exceed v cc + 0.3 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc * 1 v ss C 0.3 v ss + 7.0 v avrh* 1 avrl v ss C 0.3 v ss + 7.0 v input voltage* 2 v i v ss C 0.3 v cc + 0.3 v output voltage* 2 v o v ss C 0.3 v cc + 0.3 v l level output current i ol ? 15 ma l level total output current s i ol ? 50 ma h level output current i oh ? C4 ma h level total output current s i oh C48ma power consumption p d +400mw operating temperature t a C40 +85 c storage temperature t stg C55 +150 c parameter symbol value unit remarks min. max. power supply voltage v cc 4.0 5.5 v normal operation 2.7 5.5 v maintaining the stop status h level input voltage v ih 0.7 v cc v ss + 0.3 v except v ihs v ihs 0.8 v cc v ss + 0.3 v hysteresis inputs l level input voltage v il v ss C 0.3 0.8 v except v ils v ils v ss C 0.3 0.2 v cc v hysteresis inputs operating temperature t a C40 +85 c 47 mb90620a series 3. dc characteristics (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. h level output voltage v oh v cc = 4.5 v i oh = C4.0 ma v cc C 0.5 v l level output voltage v ol v cc = 4.5 v i oh = C4.0 ma 0.4v input leakage current i il v cc = 5.5 v 49 mb90620a series 0.8 v cc 0.2 v cc t cf t cr t c p wl p wh ? clock timing 5.5 4.0 2.7 1.5 3 8 12 f cp (mhz) normal operation range 12 8 4 0 3 4 8 12 16 24 f c (mhz) relationship between internal operation clock frequency and power supply voltage multiply by 3 multiply by 2 multiply by 1 no multiplier internal clock source oscillation clock f c (mhz) relationship between source oscillation frequency, internal operating clock frequency power supply v cc (v) internal clock f cp (mhz) pll operation assurance range : operation assurance range : pll operation assurance range ? pll operation assurance range mb90620a series 50 (2) reset input timing (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) (3) power-on reset (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 4 t c ns parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 30ms power supply cut-off time t off v cc 1ms rst 0.2vcc 0.2vcc t rstl hoding ram data 2.25 v t r 0.2 v v cc 5.0 v 2.7 v v ss v cc it is recommended that the rate of increase in the voltage be kept to no more than 50 mv/ms. if power supply voltage needs to be changed in the course of operation, a smooth voltage rise is recommended by suppressing the voltage variation as shown below. also, do not use the pll clock when varying the voltage. however, the supply voltage can be changed when using the pll clock if the voltage drops by less than 1 mv/s. 51 mb90620a series (4) uart timing (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance added to pins during testing. ?t cp is the internal operating clock cycle time (unit: ns). ? the values in the table are target values. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc for internal shift clock mode output pin, c l = 80 pf+1 ttl 8 t cp ns sck0 ? sot0 delay time t slov C80 80 ns valid sin0 ? sck0 - t ivsh 100ns sck0 - ? valid sin0 hold time t shix 60ns serial clock h pulse width t shsl for external shift clock mode output pin, c l = 80 pf+1 ttl 4 t cp ns serial clock l pulse width t slsh 4 t cp ns sck0 ? sot0 delay time t slov 150ns valid sin0 ? sck0 - t ivsh 60ns sck0 - ? valid sin0 hold time t shix 60ns mb90620a series 52 sck0 sot0 sin0 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v 2.4 v t scyc t slov t ivsh t shix sck0 sot0 sin0 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shsl t slsh t slov t ivsh t shix ? internal shift clock mode ? external shift clock mode 53 mb90620a series (5) extended serial i/o timing (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? c l is the load capacitance added to pins during testing. ?t xmcyl is the internal operation clock cycle time (unit: ns). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc 8 t xmcyl ns for internal shift clock mode output pin, c l = 80 pf+1 ttl sck1 ? sot1 delay time t slov v cc = 5.0 v 10% 80 ns valid sin1 ? sck1 - t ivsh 1 t xmcyl ns sck1 - ? valid sin1 hold time t shix 1 t xmcyl ns serial clock h pulse width t shsl v cc = 5.0 v 10% 230 ns for external shift clock mode output pin, c l = 80 pf max. 2 mhz serial clock l pulse width t slsh v cc = 5.0 v 10% 230 ns sck1 ? sot1 delay time t slov 2 t xmcyl ns valid sin1 ? sck1 - t ivsh 1 t xmcyl ns sck1 - ? valid sin1 hold time t shix 1 t xmcyl ns sck1 sot1 sin1 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v 2.4 v t scyc t slov t ivsh t shix sck1 sot1 sin1 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shsl t slsh t slov t ivsh t shix ? internal shift clock mode ? external shift clock mode mb90620a series 54 (6) timer input timing (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) (7) trigger input timing (v cc = 4.0 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh t tiwl tio0 to tio2 4 t cp ns parameter symbol pin name condition value unit remarks min. max. trigger input width t trwh t trwl adt trg 4 t cp ns a/d trigger 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trwh t trwl 55 mb90620a series 5. a/d converter electrical characteristics (av cc = v cc = +2.7 v to 5.5 v, av ss = v ss = 0.0 v, +2.7 v avrh C avrl, t a = C40 c to +85 c) * : current when the a/d converter is not operating and the cpu is stopped (when v cc = av cc = avrh = +5.5 v) notes: the smaller | avrh C avrl |, the greater the error would become relatively. the output impedance of the external circuit for the analog input must satisfy the following conditions: the output impedance of the external circuit should be less than approximately 7 k w . if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 5 m s @ at a machine clock of 12 mhz). parameter sym- bol pin name value unit min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 1.5 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to an3 C1.5 +0.5 +2.5 lsb full-scale transition voltage v fst an0 to an3 avrh C 3.5 avrl C 1.5 avrh + 0.5 lsb conversion time 8.16 m s analog port input current i ain an0 to an3 10 m a analog input voltage v ain an0 to an3 avrl avrh v reference voltage avrh avrl av cc v avrl avrh v power supply current i a av cc 5ma i ah av cc 5* m a reference voltage supply current i r av cc 200 m a i rh av cc 5* m a interchannel disparity an0 to an3 4 lsb comparator analog input r on0 r on1 c 1 c 0 r on0 = approx. 1.5 k w (5.0 v) r on1 = approx. 1.0 k w (5.0 v) c 0 = approx. 60 pf (5.0 v) c 1 = approx. 4 pf (5.0 v) ? analog input circuit model diagram note: use the values shown as guides only. mb90620a series 56 6. a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter. if the resolution is 10 bits, the analog voltage can be resolved into 2 10 = 1024 steps. ? total error the deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. ? linearity error the deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 ? 00 0000 0001) and the full scale transition point (11 1111 1110 ? 11 1111 1111). ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value digital output 1111 1111 1111 1110 0000 0001 0000 0000 0000 0010 v ot v nt v (n+1)t v fst (1 lsb n + v ot ) analog input linearity error 1 lsb = 1022 v fst ?v ot linearity error = 1 lsb v nt ?(1 lsb n + v ot ) [lsb] 11 11 00 00 00 1 lsb v (n + 1)t ?v nt ?1 [lsb] differential linearity error = 57 mb90620a series n example characteristics (continued) 60 50 40 30 20 10 0 ?0 25 85 temperature ( c) current value (ma) power supply current vs temperature characteristics example mb90623a/622a current consumption characteristics example pll stop external oscillator: 8 mhz (internal 4 mhz) power supply voltage: 5.0 v 60 50 40 30 20 10 0 ?0 25 85 temperature ( c) current value (ma) power supply current vs temperature characteristics example mb90623a/622a current consumption characteristics example pll stop external oscillator: 16 mhz (internal 8 mhz) power supply voltage: 5.0 v 60 50 40 30 20 10 0 ?0 25 85 temperature ( c) current value (ma) power supply current vs temperature characteristics example mb90623a/622a current consumption characteristics example pll stop external oscillator: 24 mhz (internal 12 mhz) power supply voltage: 5.0 v mb90620a series 58 (continued) 60 50 40 30 20 10 0 4 12 8 internal frequency (mhz) current value (ma) operation frequency vs power supply current characteristics example mb90623a/622a current consumption characteristics example pll stop external oscillator/2 = internal frequency power supply voltage: 5.0 v temperature: 25 c 8 7 6 5 4 3 2 1 0 4.0 4.5 5.5 5.0 power supply voltage (v) current value (ma) sleep mode power supply current characteristics example sleep mode current consumption characteristics example external oscillator: 4 mhz temperature: 25 c ext 8 mhz (internal 4 mhz) ext16 mhz (internal 8 mhz) ext20 mhz (internal 10 mhz) ext24 mhz (internal 12 mhz) 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 power supply voltage (v) power supply current (ma) power supply voltage vs power supply current characteristics example power supply voltage vs power supply current characteristics example temperature: 25 c 59 mb90620a series (continued) 10 9 8 7 6 5 4 3 2 1 0 4.0 4.5 5.0 5.5 power supply voltage (v) current value (ma) sub operation mode power supply current characteristics example sub operation mode current consumption characteristics example operation frequency: 32 khz temperature: 25 c 16 14 12 10 8 6 4 2 0 4.0 4.5 5.5 5.0 power supply voltage (v) current value (ma) watch mode power supply current characteristics example watch mode current consumption characteristics example operation frequency: 32 khz temperature: 25 c multiply by 1 (internal 4 mhz) multiply by 2 (internal 8 mhz) multiply by 3 (internal 12 mhz) 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 power supply voltage (v) power supply current (ma) power supply current characteristics during pll operation power supply current characteristics during pll operation oscillation frequency: 4 mhz temperature: 25 c mb90620a series 60 (continued) 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 4.0 4.5 5.0 5.5 power supply voltage (v) current value (ma) pseudo-watch mode power supply current characteristics example pseudo-watch mode current consumption characteristics example oscillation frequency: temperature: 25 c main 4 mhz sub 32 khz oscillation 2 mhz oscillation 4 mhz oscillation 6 mhz 30 25 20 15 10 5 0 none interval (1/3) interval (1/6) interval (1/9) power suppl y volta g e ( v ) power supply current (ma) cpu intermittent mode power supply current characteristics cpu intermittent mode power supply current characteristics power supply voltage: 5.0 v temperature: 25 c 61 mb90620a series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. mb90620a series 62 table 2 explanation of symbols in tables of instructions symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address 63 mb90620a series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2 mb90620a series 64 table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +01+01+02 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +11+42+84 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3 65 mb90620a series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90620a series 66 table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw al, ah /movw @a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C 67 mb90620a series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C mb90620a series 68 table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ r g boperation l h a h istnzvc rm w cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C 69 mb90620a series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C mb90620a series 70 table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C * 71 mb90620a series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ r g boperation l h a h istnzvc rm w neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation l h a h istnzvc rm w nrml a, r0 2 * 1 10 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C mb90620a series 72 table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g b operation l h a h istnzvc rm w rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C 73 mb90620a series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15 (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15 (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90620a series 74 table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 9 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C 75 mb90620a series table 20 other control instructions (byte/word/long word) [28 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90620a series 76 table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation l h a h istnzvc rm w movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C 77 mb90620a series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ r g boperation l h a h istnzvc rm w swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ r g b operation l h a h istnzvc rm w movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C mb90620a series 78 n ordering information model package remarks mb90622pfv mb90623pfv mb90p623pfv 100-pin plastic lqfp (fpt-100p-m05) 79 mb90620a series n package dimensions c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. dimension in mm (inches) (mounting height) 100-pin plastic lqfp (fpt-100p-m05) mb90620a series 80 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. |
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